Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same

ABSTRACT

One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include providing a substrate having a front side and a back side, the substrate including a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate; etching the substrate on the back side of the substrate to remove at least a portion of the substrate on the back side; forming a first dielectric layer covering the back side of the substrate and extending away from the front side of the substrate; and forming a through silicon via (TSV) adjacent to the DT capacitor, the TSV extending through the first dielectric layer toward the front side of the substrate.

BACKGROUND Technical Field

The present disclosure relates to integrated circuit structures, andmore particularly, to an integrated circuit structure, such as anintegrated circuit structure including an interposer, having a deeptrench (DT) capacitor and through-silicon via (TSV) and method offorming the same.

Related Art

Interposers are thinned silicon die which are interposed between activeor logic silicon and a packaging substrate. Interposers enableheterogeneous integration of die from various technology nodes to createan optimal cost-performance solution. Interposers with deep trench (DT)capacitors are capable of delivering powerful reductions inmid-frequency noise, thus, further enhancing system performance.Interposers may include through-silicon vias (TSVs) for joining chips(or dies) by vertically interconnecting through the interposer andfunctioning as components of an integrated circuit.

Stacking chips in comparison to wire bonding, reduces inductive losseswhich increases speed of data exchange. Since TSVs allow for shorterinterconnects between the dies, there is a reduced power consumptioncaused by the conventional long horizontal wiring. As a result, TSVsallow much higher input/output density than wire bonding, which consumesmuch more space.

In this manner, TSVs allow multiple integrated circuit chips to bestacked together, allowing greater amounts of information to be passedbetween the chips. For example, integrated circuit chips and memorydevices, which typically reside side-by-side on a silicon wafer, can bestacked on top of one another with the advent of the TSVs. Stacking theintegrated circuit chips with the memory devices dramatically reducesthe size of the overall chip package and boost speeds at which dataflows among the functions on the chip. Signal transmission through TSVsin conventional silicon interposers is not as efficient as with othermaterials, such as dielectric materials. However, DT capacitors cannotbe fabricated in as fine dimensions in dielectric materials as they canbe within silicon.

SUMMARY

A first aspect of the disclosure provides for a method of forming anintegrated circuit structure. The method may include: providing asubstrate having a front side and a back side, the substrate including:a deep trench (DT) capacitor within the substrate extending toward theback side of substrate, and a through silicon via (TSV) adjacent to theDT capacitor within the substrate extending toward the back side of thesubstrate, the TSV including a metal substantially surrounded by a linerlayer and an insulating layer substantially surrounding the liner layer;etching the back side of the substrate to expose the TSV on the backside of the substrate; and forming a first dielectric layer covering theexposed TSV on the back side of the substrate and extending away fromthe front side of the substrate.

A second aspect of the disclosure provides for a method of forming anintegrated circuit structure. The method may include: providing asubstrate having a front side and a back side, the substrate including:a deep trench (DT) capacitor within the substrate extending toward theback side of the substrate, etching the substrate on the back side ofthe substrate to remove at least a portion of the substrate on the backside; forming a first dielectric layer covering the back side of thesubstrate and extending away from the front side of the substrate; andforming a through silicon via (TSV) adjacent to the DT capacitor, theTSV extending through the first dielectric layer toward the front sideof the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of this disclosure will be more readilyunderstood from the following detailed description of the variousaspects of the invention taken in conjunction with the accompanyingdrawings that depict various embodiments of the disclosure, in which:

FIGS. 1-3 show cross-sectional views of a wafer undergoing preliminaryaspects of a method according to an embodiment of the disclosure.

FIGS. 4-8 show cross-sectional views of a wafer undergoing aspects of amethod according to an embodiment of the disclosure.

FIGS. 9-15 show cross-sectional views of a wafer undergoing aspects of amethod according to other embodiments of the disclosure.

FIGS. 16-25 show cross-sectional views of a wafer undergoing aspects ofa method according to other embodiments of the disclosure.

FIGS. 26-31 show cross-sectional views of a wafer undergoing aspects ofa method according to other embodiments of the disclosure.

It is noted that the drawings of the invention are not to scale. Thedrawings are intended to depict only typical aspects of the invention,and therefore should not be considered as limiting the scope of theinvention. In the drawings, like numbering represents like elementsbetween the drawings.

DETAILED DESCRIPTION

The present disclosure relates to integrated circuit structures, andmore particularly, to an integrated circuit structure, such as aninterposer, having a deep trench (DT) capacitor and through-silicon via(TSV) and method of forming the same. For ease of illustration, thedisclosure is discussed as employed for interposers. However, it is tobe understood that the disclosure is equally applicable to full devicestructures, e.g., an active device chip in combination with aninterposer, three-dimensional logic chip, etc., as well. Signaltransmission through TSVs in conventional silicon or semiconductorinterposers is not as efficient as with other materials, such asdielectric materials. However, DT capacitors cannot be fabricated in asfine dimensions in dielectric materials as they can be within silicon orsemiconductor. The present disclosure provides for a method andintegrated circuit structure that replaces much of the silicon orsemiconductor on an interposer with a dielectric material, e.g.,polyimide, in order to increase signal transmission through TSVs.Additionally, this method is performed subsequent to the formation of DTcapacitors. Therefore, DT capacitors can be fabricated with finedimensions in silicon before a percentage of the silicon is replacedwith dielectric material. The percentage of the silicon that is removedthat surrounds the DT capacitors can be determined by a function of DTcapacitance requirements versus alpha particles and dielectric leakageloss. For maximum capacitance of the DT capacitors, minimal removaloccurs surrounding the DT capacitors, thus the DT capacitors may befully buried in silicon. As such, the present disclosure both maintainsthe benefits of having DT capacitors with fine dimensions and increasessignal performance of TSVs.

FIG. 1 shows a cross-sectional view of a preliminary wafer 100, e.g., apassive silicon interposer, that is to undergo aspects of a methodaccording to embodiments of the disclosure as described herein. Wafer100 may include a substrate 110 having a front side 102 and a back side104. Substrate 110 may include a semiconductor layer 112. Overlyingsemiconductor layer 112 as shown in FIG. 1 may be a buried insulatorlayer 114, and overlying buried insulator layer 114 may be asemiconductor-on-insulator (SOI) layer 116. However, in otherembodiments, (not shown) substrate 110 may include a bulk siliconsubstrate.

Semiconductor layer 112 and SOI layer 116 may each include but are notlimited to silicon, germanium, silicon germanium, silicon carbide, andthose consisting essentially of one or more III-V compoundsemiconductors having a composition defined by the formulaAl_(X1)Ga_(X2)In_(X3)As_(Y1)P_(Y2)N_(Y3)Sb_(Y4), where X1, X2, X3, Y1,Y2, Y3, and Y4 represent relative proportions, each greater than orequal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relativemole quantity). Other suitable substrates include II-VI compoundsemiconductors having a composition Zn_(A1)Cd_(A2)Se_(B1)Te_(B2), whereA1, A2, B1, and B2 are relative proportions each greater than or equalto zero and A1+A2+B1+B2=1 (1 being a total mole quantity). Buriedinsulator layer 114 may include silicon oxide (BOX layer) or otherinorganic dielectric materials. As mentioned, substrate 110 may includea bulk silicon substrate in other embodiments.

Wafer 100 may also include a back-end-of-the-line (BEOL) region 120 overfront side 102. BEOL region 120 may include a transition region 122representing the transition from front-end-of-the-line (FEOL) havingdevice structures to BEOL construction. FEOL constructions may residewithin SOI layer 116. For example, SOI layer 116 may include integratedcircuit devices 128 (shown in phantom), or portions thereof, such as butnot limited to: transistors, resistors, interconnects etc. BEOL region120 may also include BEOL layer 124 having contacts and wiringstructures as is known in the art but shown as a single layer/materialherein for brevity. Transition region 122 facilitates the prevention ofcontaminants from BEOL region 120 entering into the FEOL region.Generally, refractory metals and high temperature diffusion barriersagainst copper and mobile ions, are used in transition region 122. BEOLprocessing includes the series of processes in which wiring is formed toconnect to the semiconductor devices formed during FEOL processing. BEOLprocessing generally begins when the first layer of metal wiring isformed on the wafer subsequent to transition region 122. In sometechnologies, the transition region may be called the MOL (middle ofline), which connects the FEOL to the BEOL.

Wafer 100 may also include passive devices such as at least one deeptrench (DT) capacitor 130. DT capacitors 130 may be disposed withinsubstrate 110 at front side 102 and extend from front side 102 towardback side 104. In some embodiments, DT capacitors 130 may contact BEOLregion 120. DT capacitors 130 may include a liner layer 132, e.g.,titanium nitride, tantalum nitride, tungsten nitride, tantalum,titanium, or other thermally stable material having attribute for FEOLprocessing, and an inner conductor layer 134, e.g., polysilicon or otherconductor having similar properties or capable of performing similarfunctions, within liner layer 132. DT capacitors 130 may include aninsulating layer 136 which serves as a capacitor dielectric andsubstantially surrounds liner layer 132 such that liner layer 132 issubstantially between insulating layer 136 and inner conductor layer134. Insulating layer 136 may include, for example, an oxide, such assilicon dioxide or hafnium oxide, or nitride, such as silicon nitride.Insulating layer 136, liner layer 132 and inner conductor layer 134 maybe planar with a surface of SOI layer 116 that is on front side 102. Asused herein, “substantially” refers to largely, for the most part,entirely specified or any slight deviation which provides the sametechnical benefits of the invention.

Wafer 100 may also include a through silicon via (TSV) 140. TSV 140 mayinclude a liner layer 142 and a conductive metal layer 144 substantiallysurrounded by liner layer 142. Liner layer 142 may include, but is notlimited to tantalum nitride, titanium nitride, or tungsten nitride, orother equally suitable material to improve adhesion or other structuralor electrical properties of the structure to be formed. Liner layer 142may prevent electromigration of metal from metal layer 144 into adielectric. Metal layer 144 may include copper or any other suitableconductive material such as, but not limited to, titanium, tungsten,tantalum, aluminum, or alloys thereof. TSV 140 may also include aninsulating layer 146 substantially surrounding liner layer 142 such thatliner layer 142 is substantially between insulating layer 146 and metallayer 144. Insulating layer 146 may include, for example, an oxide, suchas silicon dioxide or hafnium oxide, or nitride, such as siliconnitride.

Wafer 100 may be initially formed by forming buried insulator layer 114over semiconductor layer 112 and SOI layer 116 over buried insulatorlayer 114 such as by deposition or wafer bonding, e.g., separation byimplantation of oxygen (SIMOX). As used herein, the term “depositing”may include any now known or later developed technique appropriate fordeposition, including but not limited to, for example: chemical vapordeposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD),semi-atmosphere CVD (SACVD) high density plasma CVD (HDPCVD), rapidthermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reactionprocessing CVD (LRPCVD), metalorganic CVD (MOCVD), sputteringdeposition, ion beam deposition, electron beam deposition, laserassisted deposition, thermal oxidation, thermal nitridation, spin-onmethods, physical vapor deposition (PVD), atomic layer deposition (ALD),chemical oxidation, molecular beam epitaxy (MBE), plating, andevaporation.

Further, trench openings or discrete columnar openings (not shown) maybe formed in substrate 110 to facilitate the formation of DT capacitors130. For ease of description, the term trench openings may represent allsuch openings. A mask (not shown) may be formed over SOI layer 116 andpatterned such that portions of the mask are removed to expose portionsof SOI layer 116 thereunder where DT capacitors 130 are to be formed.Exposed portions of SOI layer 116, including buried insulator layer 114and semiconductor layer 112 thereunder, may then be etched to form thetrench openings. Subsequently, the remaining portions of the mask may beremoved. Liner layer 132 may be formed, e.g., deposited, within thetrench openings to substantially line the trench openings. Innerconductor layer 134 may be formed, e.g., deposited, within the trenchopenings over liner layer 132. DT capacitors 130 may also includeinsulating layer 136. In such an embodiment, insulating layer 136 may beformed, e.g., deposited, within the trench openings to substantiallyline the trench openings prior to the formation of liner layer 132.Insulating layer 136, liner layer 132 and inner conductor layer 134 maybe planarized to a surface of SOI layer 116 at front side 102.

The term “mask” may be given to a layer of material which is appliedover an underlying layer of material, and patterned to have openings, sothat the underlying layer can be processed where there are openings.After processing the underlying layer, the mask may be removed. Commonmasking materials are either organic, e.g., a photoresist (resist), orinorganic, e.g., an oxide and nitride. Inorganic materials such as oxideor nitride are usually considered to be a “hard mask.” Many times thishard mask may be used in conjunction with a soft mask (resist). Thematerials for the mask may be selected based on requirements such asopacity to the laser wavelength used, and selectivity to the etchesused.

“Etching” generally refers to the removal of material from a substrate(or structures formed on the substrate), and is often performed with amask in place so that material may selectively be removed from certainareas of the substrate, while leaving the material unaffected, in otherareas of the substrate. There are generally two categories of etching,(i) wet etch and (ii) dry etch. Wet etch is performed with a chemical(such as an acid) which may be chosen for its ability to selectivelydissolve a given material (such as oxide), while leaving anothermaterial (such as polysilicon) relatively intact. The ability toselectively etch particular materials is fundamental to manysemiconductor fabrication processes. A wet etch will generally etch ahomogeneous material (e.g., oxide) isotropically, but a wet etch mayalso etch single-crystal materials (e.g. silicon wafers)anisotropically. Dry etch may be performed using a plasma. Plasmasystems can operate in several modes by adjusting the parameters of theplasma. Ordinary plasma etching produces energetic free radicals,neutral or charged, that react at the surface of the wafer. Sinceneutral particles attack the wafer from all angles, this process isisotropic. Ion milling, or sputter etching, bombards the wafer withenergetic ions of noble gases which approach the wafer approximatelyfrom one direction, and therefore this process is highly anisotropic.Reactive-ion etching (RIE) operates under conditions intermediatebetween sputter and plasma etching and may be used to produce deep,narrow features, such as STI trenches.

Planarization refers to various processes that make a surface moreplanar (that is, more flat and/or smooth). Chemical-mechanical-polishing(CMP) is one currently conventional planarization process whichplanarizes surfaces with a combination of chemical reactions andmechanical forces. CMP uses slurry including abrasive and corrosivechemical components along with a polishing pad and retaining ring,typically of a greater diameter than the wafer. The pad and wafer arepressed together by a dynamic polishing head and held in place by aplastic retaining ring. The dynamic polishing head is rotated withdifferent axes of rotation (that is, not concentric). This removesmaterial and tends to even out any “topography,” making the wafer flatand planar.

Other currently conventional planarization techniques may include: (i)oxidation; (ii) chemical etching; (iii) taper control by ion implantdamage; (iv) deposition of films of low-melting point glass; (v)resputtering of deposited films to smooth them out; (vi) photosensitivepolyimide (PSPI) films; (vii) new resins; (viii) low-viscosity liquidepoxies; (ix) spin-on glass (SOG) materials; gas-cluster ion-beam;and/or (x) sacrificial etch-back.

In one method of construction, additional openings (not shown) may beformed in substrate 110 to facilitate the formation of TSV 140 adjacentto at least one DT capacitor 130. That is, a mask (not shown) may beformed over SOI layer 116 and patterned such that portions of the maskare removed to expose portions of SOI layer 116, including buriedinsulator layer 114 and semiconductor layer 116 thereunder, where TSV140 is to be formed. The exposed portions of SOI layer 116 may then beetched to form the openings, and the remaining portions of the mask maybe removed. Liner layer 142 may be formed, e.g., deposited, within theopenings to substantially line the openings. Metal layer 144 may beformed, e.g., deposited, within the openings over liner layer 142 tosubstantially fill the opening. TSV 140 may also include insulatinglayer 146. In such an embodiment, insulating layer 146 may be formed,e.g., deposited, within the opening to substantially line the openingprior to the formation of liner layer 142. Insulating layer 146, linerlayer 142 and metal 144 may be planarized to a surface of SOI layer 116at front side 102. This method is typically denoted as a middle of lineTSV integration. Subsequent processing for the back end region continuesthe structure to termination.

Further, BEOL region 120 may be formed over SOI layer 116 on front side102 of substrate 110 extending away from back side 104. That is, BEOLlayer 124 may be formed as known in the art to include several metalwiring levels that facilitate the connection to both active and passivesemiconductor devices within the structure including the transitionregion 122 from BEOL layer 124 and FEOL region, i.e., SOI layer 116, isformed over SOI layer 116, DT capacitors 130, and TSV 140. In otherembodiments (not shown), TSV 140 may be formed at a desired time duringformation of BEOL region 120 depending on the desired application ofwafer 100. In such an embodiment, TSV 140 may extend at least partiallythrough BEOL region 120.

In another method of construction, additional openings (not shown) maybe formed in substrate 110 to facilitate the formation of TSV 140adjacent to at least one DT capacitor 130. That is, a mask (not shown)may be formed over BEOL 124 and patterned such that portions of the maskare removed to expose portions of BEOL layer 124, with subsequentexposure of transition region 122, SOI layer 116, buried insulator layer114, and semiconductor layer 116 thereunder, where TSV 140 is to beformed. The exposed portions of BEOL 124 may then be etched to form theopenings, and the remaining portions of the mask may be removed. Linerlayer 142 may be formed, e.g., deposited, within the openings tosubstantially line the openings. Metal layer 144 may be formed, e.g.,deposited, within the openings over liner layer 142 to substantiallyfill the opening. TSV 140 may also include insulating layer 146. In suchan embodiment, insulating layer 146 may be formed, e.g., deposited,within the opening to substantially line the opening prior to theformation of liner layer 142. Insulating layer 146, liner layer 142 andmetal 144 may be planarized to a surface of SOI layer 116 at front side102. This method is typically denoted as back end of line TSVintegration.

Referring now to FIG. 2, a handle wafer 148 may be formed over frontside 102 such that handle wafer 148 covers BEOL region 120 and extendsaway from back side 104. Handle wafer 148 may be bonded to wafer 100using standard processes, such as temporary adhesive bonding. As knownin the art, handle wafer 148 may include, for example, bulk silicon orglass. Handle wafer 148 provides mechanical support to wafer 100 suchthat wafer 100 may be manipulated to undergo additional processing.

Referring to FIG. 3, wafer 100 may be flipped or turned over such thatback side 104 may undergo additional processing. As shown in FIG. 4,substrate 110 may be etched back to expose TSV 140. FIG. 4 showssubstrate 110 being etched to just above DT capacitors 130 such that DTcapacitors 130 remain encased in or surrounded by substrate 110.However, it is to be understood that substrate 110 may be etched to anydesirable depth which may be above the DT capacitor 130 termination orbelow the DT capacitor 130 termination, without departing from aspectsof the disclosure. While many conventional structures utilize thinlayers of SOI on the order of approximately 50 nanometers (nm) toapproximately 100 nm, embodiments of the disclosure as described hereinare not so limited. The RIE process can be selective to semiconductorlayer 112 over buried insulator layer 114 by proper parameter selection.For example, sulfur hexafluoride gas can be used to etch semiconductorlayer 112 and not aggressively etch buried insulator layer 114. Powerand chemistry parameters can be varied to enhance semiconductor layer112 selectivity versus buried insulator layer 114 selectivity. DuringRIE, dielectrics or insulators are not etched or may be very minimallyetched. This etch process is selective to inorganic materials, such assemiconductor layer 112. In this way, buried insulator layer 114 may actas a natural stop for the etch process thereby protecting semiconductordevices 128. Additionally, since DT capacitors 130 and TSV 140 mayinclude insulating layers 136, 146, DT capacitors 130 and TSV 140 willnot be harmed during the etch process. In some embodiments, it may bedesirable to etch substrate 110 such that a portion of semiconductorlayer 112 remains. In other embodiments, such as with a bulk siliconsubstrate where a buried insulator layer is not present, substrate 110may be etched such that a majority of the bulk silicon substrate can beremoved. However, in any instance, substrate 110 should not be etched toexpose devices 128. That is, substrate 110 should be etched to athickness that does not cause damage to devices 128. Substrate 110 maybe etched to a thickness at just about or above semiconductor devices128, thereby ensuring that semiconductor devices 128 are not affectedduring the etch. In some embodiments, a timed etch may be employed suchthat substrate 110 undergoes etching for a particular duration of timeat a particular rate that terminates prior to semiconductor devices 128.The time for the etch may be determined by the etch rate of the materialused for substrate, and the desired etch depth, taking intoconsideration the resistance to etch of the dielectric layers. Thepercentage of the substrate 110 that surrounds DT capacitors 130 may bedetermined by a function of DT capacitance requirements versus desiredeffect of alpha particles and dielectric leakage loss. For maximumcapacitance of DT capacitors 130, minimal removal occurs surrounding DTcapacitors 130. Thus, DT capacitors 130 may be fully buried in substrate110.

Referring now to FIG. 5, a dielectric layer 150 may be formed, e.g.,deposited, over substrate 110, including parts of TSV 140. In otherembodiments, dielectric layer 150 may be formed over semiconductor layer112 where DT capacitors 130 remain encased in substrate 110.Additionally, where DT capacitors 130 are fully exposed, dielectriclayer 150 may be formed over buried insulator layer 114. In anyembodiment, dielectric layer 150 may be formed on back side 104extending away from front side 102. Dielectric layer 150 may includepolymers and/or organic insulators such as polyimide (such as standardKapton® or advanced Kapton® available from E. I. du Pont de Nemours andCompany), polystyrene, polypropylene, polyethylene, polycarbonate,and/or inorganic materials such as silicon oxide (SiO₂) and aluminumoxide (Al₂O₃). Other dielectric materials can include, e.g., siliconnitride, fluorinated silicon dioxide (FSG), hydrogenated siliconoxycarbide (SiCOH), porous SiCOH, boro-phospho-silicate glass (BPSG),silsesquioxanes, near frictionless carbon (NFC), carbon doped oxides(i.e., organosilicates) that include atoms of silicon, carbon, oxygen,and/or hydrogen, thermosetting polyarylene ethers, SiLK (a polyaryleneether available from Dow Chemical Corporation), a spin-on silicon-carboncontaining polymer material available from JSR Corporation, flex epoxyadhesive, flex acrylic adhesive, Teflon®, other low dielectric constant(<3.9) materials, or layers thereof. Dielectric layer 150 may be formedby chemical or plasma reactions designed to produce the desired materialand the process may be designed to produce a layer planar with an uppersurface of TSV 140. In some embodiments, dielectric layer 150 may beformed to completely surround TSV 140. Subsequently, dielectric layer150 may be planarized to a surface of TSV 140 that is farthest fromfront side 102.

Referring now to FIG. 6, in the case where liner layer 142 is notexposed at a surface of dielectric layer 150 farthest from front side102, a portion 152 (shown in phantom) of insulating layer 146 may beremoved from a surface of TSV 140 that is farthest from front side 102to expose liner layer 142. That is, portion 152 of insulating layer 146may be etched to expose liner layer 142 over back side 104. Portion 152of insulating layer 146 may be removed via a RIE process or a wet etchprocess that is selective to the insulating layer 146 and leavesdielectric layer 150 substantially unaffected. Additionally, thisselective etch process may be performed for a particular duration andrate such that insulator layer 146 on sidewalls of TSV 140 remainsubstantially unaffected. The duration and rate can be determined basedupon the materials that are used for insulating layer 146 and dielectriclayer 150 and type of etch process employed. It is understood that othermethods such as CMP may also be used to expose a liner layer 142 to givea resultant surface as shown in FIG. 5.

FIG. 7 shows a resulting integrated circuit structure 190, e.g.,interposer, after a conductive pad 156 has been formed on back side ofwafer 100 (FIG. 6). That is, after portion 152 (FIG. 6) of insulatinglayer 146 is removed, conductive pad 156 may be formed over TSV 140 suchthat conductive pad 156 is formed over back side 104 and extends awayfrom front side 102. Conductive pad 156 may be formed via deposition ofa liner, e.g., any of the liner layers discussed herein, and aconductor, e.g., copper, patterning of a mask thereover, and etching.Conductive pad 156 may contact liner layer 142 of TSV 140. In this way,appropriate electrical connection is ensured between conductive pad 156and TSV 140.

Still referring to FIG. 7, resulting integrated circuit structure 190may include dielectric layer 150 extending from substrate 110 in adirection away from a front side 102. Integrated circuit structure 190may also include BEOL region 120 extending from substrate 110 in adirection away from a back side 104. At least one DT capacitor 130 maybe disposed within substrate 110 and may extend toward BEOL region 120and toward back side 104. DT capacitors 130 may each be encased bysubstrate 110 as shown in FIG. 7. However, in other embodiments, DTcapacitors may be at least partially disposed within substrate 110 andpartially disposed within dielectric layer 150. Further, integratedcircuit structure 190 may include TSV 140 adjacent to at least one DTcapacitor 130 and extending from BEOL region 120 through dielectriclayer 150 and substrate 110 away from front side 102. In otherembodiments, TSV 140 may be formed during the formation of BEOL region120 and may be at least partially disposed within BEOL region 120.Additionally, integrated circuit structure 190 may include a conductivepad 156 over TSV 140 and dielectric layer 150 over back side 104extending from front side 102. Integrated circuit structure 190 hasimproved performance in that DT capacitors 130 were fabricated insilicon, e.g., substrate 110, and TSV 140 has increased signaltransmission due to being at least partially disposed within dielectriclayer 150. That is, signal retention is improved by minimizing theamount of silicon that is surrounding TSV 140.

In some embodiments, it may be desirable to include additional wiringlevels within integrated circuit structure 190. In those embodiments,another dielectric layer 164 may be formed over conductive pad 156 asshown in FIG. 8. That is, dielectric layer 164 may be formed over backside 104 extending away from front side 102. Dielectric layer 164 maycover conductive pad 156 and at least a portion of dielectric layer 150over back side 104. Dielectric layer 164 may include any of thedielectric layer materials listed relative to dielectric layer 150 aswell as any other dielectric material known in the art. Further, aconnection 170 may be formed within dielectric layer 164, e.g., viapatterning a mask (not shown), etching a dielectric layer 164,depositing liner layer 172 and conductive metal layer 174, andplanarization. Connection 170 may be formed such that it contactsconductive pad 156. Connection 170 may include a liner layer 172 and aconductive metal layer 174. Liner layer 172 may include any of the linerlayer materials discussed herein. Metal layer 174 may include any of theconductive metal layer materials discussed herein. Liner layer 172 maybe optionally removed or thinned at a surface of connection 170 closestto conductive pad 156 before formation of metal layer 174 to reduceresistivity. Further, another conductive pad 178 similar to conductivepad 156 may be formed over dielectric layer 164 such that it contactsconnection 170 and extends away from front side 102. As shown,connection 170 extends from conductive pad 156 toward conductive pad 178in a direction away from front side 102.

FIGS. 9-15 show integrated circuit structure 100 (FIG. 9) according toanother embodiment of the disclosure. In this embodiment, dielectriclayer 150 may be formed over TSV 140 and substrate 110 including DTcapacitors 130 as described with reference to FIG. 5. However, a wiremay be formed within dielectric layer 150. In this embodiment,dielectric layer 150 may be formed by depositing a plurality of layers(not individually shown) and performing a dry or wet surface treatmentsuch as a chemical etch, ash, or plasma in between the deposition ofeach layer so that the subsequent layer may have greater adhesion to theprevious layer. During the formation of the plurality of layers, a wire220 (FIG. 10) may be formed therein using standard photolithographytechniques. Whilst in prior structures, a plurality of layers may havebeen used to form dielectric layer 150, in the case where wire 220 isinclude, a minimum of two such layers must be utilized. For example, amask (not shown) may be formed over one of the layers in the pluralityof layers of dielectric layer 150. The mask may be patterned to expose aportion of one of the plurality of layers substantially adjacent to TSV140. The exposed portion may be etched to form an opening or trench 202as shown in FIG. 9 and the mask may be removed. In some embodiments (notshown), opening 202 may be formed immediately adjacent to TSV 140 suchthat electrical connection is provided between the wire that is to beformed within opening 202 and TSV 140. In other embodiments (shown),opening 202 may be formed within dielectric layer 150 such that opening202 is not immediately adjacent to and is separated from TSV 140. Inthis embodiment, the wire to be formed within opening 202 will not bedirectly electrically connected to TSV 140, rather, the wire isconnected to TSV 140 via a conductive pad and connection as will bedescribed herein.

A liner layer 222 may be formed within opening 202 to substantially coatopening 202 as shown in FIG. 10. Subsequently, a metal layer 224 may beformed within opening 202 over liner layer 222 to substantially fillopening 202. Any portion of liner layer 222 and/or metal layer 224 thatis disposed outside of opening 202 may be removed via a planarizationtechnique, e.g., CMP. Further, additional layers of dielectric layer 150may be formed to substantially surround wire 220 as shown in FIG. 11.Dielectric layer 150 may be formed such that it is planar with a surfaceof TSV 140 farthest from front side 102. In other embodiments,Dielectric layer 150 may be planarized to a surface of TSV 140 that isfarthest from front side 102.

As shown in FIG. 12, another opening 232 may be formed within dielectriclayer 150. A mask (not shown) may be formed over the additional layersof dielectric layer 150 and patterned to expose a portion of theadditional layers that are directly over wire 220. The additional layersdirectly over wire 220 may be etched to form opening 232 to expose metallayer 224 of wire 220. A connection 240 may be formed within opening 232as shown in FIG. 13. Connection 240 may extend from wire 220 and awayfrom front side 102 to a surface of dielectric layer 150 that isfarthest from front side 102. Connection 240 may include another linerlayer 242 and metal layer 244. Liner layer 242 and metal layer 244 ofconnection 240 may include any of the materials listed herein for linerlayers or conductive metal layers. Connection 240 may be formed suchthat it is in electrical contact with wire 220. That is, liner layer 242may be formed, e.g., deposited, to substantially coat opening 232 suchthat liner layer 242 is in contact with wire 220, e.g., metal layer 224of wire 220. Additionally, metal layer 244 may be formed, e.g.,deposited, over liner layer 242 to substantially fill opening 232. Anyportion of liner layer 242 and/or metal layer 244 that is disposedoutside of opening 232 may be removed via a planarization technique,e.g., CMP. After connection 240 is formed such that it is in electricalconnection with wire 220, conductive pad 156 may be formed as describedwith respect to FIGS. 6-7 as shown in FIG. 14 to form a resultingintegrated circuit structure 290, e.g. an interposer. However, in thisembodiment, conductive pad 156 may be formed such that it is inelectrical connection with both TSV 140 and connection 240. That is,conductive pad 156 and connection 240 provide electrical connectionbetween wire 220 and TSV 140. Conductive pad 156 may be formed over TSV140, connection 240 and at least a portion of dielectric layer 150 overback side 104. In another embodiment (not shown), opening 232 may beformed and then filled with liner layer 242 and metal layer 244 at thesame time that conductive pad 156 is formed such that conductive pad 156and connection 240 include the same materials.

FIG. 15 shows resulting integrated circuit structure 290 according thisembodiment of the disclosure. As shown, additional wiring levels may beformed over conductive pad 156 over back side 104 as discussed withreference to FIG. 8. That is, dielectric layer 164 may be formed overconductive pad 156. Additionally, connection 170 may be formed withindielectric layer 164, e.g., via patterning, etching, deposition of linerlayer 172 and conductive metal 174, and planarization. Connection 170may be formed such that it contacts conductive pad 156. Further, anotherconductive pad 178 may be formed over dielectric layer 164 such that itcontacts connection 170. As shown, connection 170 extends fromconductive pad 162 toward conductive pad 178 in a direction away fromfront side 102. Integrated circuit structure 290 has improvedperformance in that DT capacitors 130 were fabricated in silicon, e.g.,substrate 110, and TSV 140 has increased signal transmission due tobeing at least partially disposed within dielectric layer 150.Additionally, this embodiment allows for additional wiring, e.g., wire220, to be formed adjacent to and electrically connected to TSV 140during formation of dielectric layer 150 resulting in finer wiring.

FIGS. 16-25 show another embodiment of the disclosure. In thisembodiment, a TSV is constructed from a back side of a substrate. Theopening for the TSV may be formed by two etch process that may allow forimproved taper control. FIG. 16 shows a cross-sectional view of apreliminary wafer 300, e.g., a passive silicon interposer. Wafer 300 mayinclude a substrate 310 having a front side 302 and a back side 304.Substrate 310 may include a semiconductor layer 312. Overlyingsemiconductor layer 312 may be a buried insulator layer 314, andoverlying buried insulator layer 314 may be a SOI layer 316.Semiconductor layer 312, buried insulator layer 314, and SOI layer 316may include any of the materials discussed herein relative tosemiconductor layer 112, buried insulator layer 114, and SOI layer 116(FIG. 1), respectively. However, in other embodiments, (not shown)substrate 310 may include a bulk silicon substrate.

Wafer 300 may also include a back-end-of-the-line (BEOL) region 320 overfront side 302. BEOL region 320 may include a transition region 322extending from SOI layer 316 away from back side 304 and a BEOL region124 extending from transition region 322 and extending away from backside 304. BEOL region 320 may include any of the materials andstructures listed with respect to BEOL region 120 (FIG. 1). Wafer 300may include other integrated circuit devices 328 (shown in phantom), orportions thereof, such as but not limited to: transistors, resistors,and interconnects, etc., within SOI layer 316. BEOL processing includesthe series of processes in which wiring is formed to connect to thesemiconductor devices formed during front-end-of-line (FEOL) processing.BEOL processing generally begins when the first layer of metal wiring isformed on the wafer.

Wafer 300 may also include passive devices such as at least one deeptrench (DT) capacitors 330. DT capacitors 330 may be disposed withinfront side 102 and extend toward back side 2014. In some embodiments, DTcapacitors 330 may contact BEOL region 320. DT capacitors 330 mayinclude a liner layer 332 and an inner conductor layer 334 substantiallysurrounded by liner layer 332. DT capacitors 330 may include insulatinglayer 336. Insulating layer 336 may be formed, e.g., deposited, withinthe trench openings to substantially line the trench openings prior tothe formation of liner layer 332. Insulating layer 336, liner layer 332and inner conductor 334 may be planarized to a top surface of SOI layer316. Liner layer 332, inner conductor layer 334, and insulating layer336 may include any of the materials discussed herein relative to linerlayer 132, inner conductor layer 134, and insulating layer 136 (FIG. 1),respectively. Wafer 300 may be formed as described herein relative toFIG. 1. However, the processes described with reference to FIG. 1relative to TSV 140 may not be included in this embodiment. As will bedescribed herein, a TSV may be formed at a later time according to theprocess of this embodiment.

Referring now to FIG. 17, a handle wafer 348 may be formed on front side302 such that handle wafer 348 covers BEOL region 320 and extends awayfrom back side 304. Handle wafer 348 may be bonded to wafer 300 usingstandard processes, such as temporary adhesive bonding. As known in theart, handle wafer 348 may include, for example, bulk silicon or glass.Handle wafer 348 provides mechanical support to wafer 300 such thatwafer 300 may be manipulated to undergo additional processing.

Referring to FIG. 18, wafer 300 may be flipped or turned over such thatback side 304 may undergo additional processing. As shown in FIG. 19,substrate 310 may be etched back to just above DT capacitors 330 suchthat DT capacitors 330 remain encased in or surrounded by substrate 310.However, it is to be understood that substrate 310 may be etched to anydesirable depth without departing from aspects of the disclosure. Insome embodiments, substrate 310 may be etched to buried insulator layer314. In this embodiment, a RIE process may be employed. The RIE processcan be selective to semiconductor layer 312 over buried insulator layer314 by proper parameter selection. For example, sulfur hexafluoride gascan be used to etch semiconductor layer 312 and not aggressively etchburied insulator layer 314. Power and chemistry parameters can be variedto enhance semiconductor layer 312 selectivity versus buried insulatorlayer 314 selectivity. During this RIE, dielectrics or insulators arenot etched or are very minimally etched. The etch process is selectiveto specific inorganic materials, such as semiconductor layer 312. Inthis way, buried insulator 314 may act as a natural stop for the etchprocess thereby protecting semiconductor devices 328. Additionally,since DT capacitors 330 includes insulating layer 336, DT capacitors 330will not be harmed during the etch process. In other embodiments, suchas where substrate 310 includes a bulk silicon substrate and a buriedinsulator layer is not present, substrate 310 may be etched such that amajority of the bulk silicon substrate can be removed. However, in anyinstance, substrate 310 should not be etched to expose devices 328. Thatis, substrate 310 should be etched to a thickness that does not causedamage to devices 328. Substrate 310 may be etched to a thickness atjust about or above semiconductor devices 328 thereby ensuring thatsemiconductor devices 328 are not affected during the etch. In someembodiments, a timed etch may be employed such that substrate 310undergoes etching for a particular duration of time at a particular ratethat terminates prior to semiconductor devices 328. The percentage ofthe substrate 310 that surrounds DT capacitors 330 that is removed maybe determined by the desired performance of DT capacitance requirementsversus effect of alpha particles and dielectric leakage loss. Formaximum capacitance of DT capacitors 330, minimal removal occurssurrounding DT capacitors 330. Thus, DT capacitors 330 may be fullyburied in substrate 310.

Referring now to FIG. 20, a dielectric layer 350 may be formed, e.g.,deposited, over substrate 310. In other embodiments, dielectric layer350 may be formed over semiconductor layer 312 where DT capacitors 330remain encased in substrate 310. Additionally, where DT capacitors 330are exposed up to the buried insulator layer 314, dielectric layer 350may be formed over 314. In any embodiment, dielectric layer 350 may beformed over back side 304 extending away from front side 102. Dielectriclayer 350 may include any of the materials discussed herein relative todielectric layer 150 (FIG. 5).

Referring now to FIG. 21, a mask 352 may be formed over dielectric layer350 on back side 304 extending away from front side 302. The materialsfor mask 352 are selected based on requirements such as opacity to thelaser wavelength used, and selectivity to the etches used. Mask 352 maybe patterned and etched to expose dielectric layer 350 to facilitate theformation of an opening 354 within dielectric layer 350 as shown in FIG.22. After dielectric layer 350 is exposed, opening 354 may be formedwithin dielectric layer 350. Opening 354 may be formed, for example, viaetching, such as RIE or laser ablation, of the dielectric layer 350 toexpose substrate 310, e.g., semiconductor layer 312. As shown in FIG.23, another etch, such as a deep RIE, e.g., a Bosch etch, may beemployed to remove portions of substrate 310 and BEOL region 320 toexpose handle wafer 348. Deep RIE etching may include a pulsed ortime-multiplexed etching. During a deep RIE etch, a mode of an isotropicetch is alternated with a deposition of a chemically inert passivationlayer (not shown). In this etch process, mask 352 (FIG. 22) may beeroded or fully removed, and dielectric layer 350 acts as an additionalmask during the etching of substrate 310 and BEOL region 320.Additionally, after this second etch process (the deep RIE), thechemically inert passivation layer may be removed and an insulatinglayer 368 may be formed, e.g., deposited, in opening 354 from dielectriclayer 350 to handle wafer 348. However, while shown and described asbeing deposited form dielectric layer 350 to handle wafer 348,insulating layer 368 may extend from handle wafer 348 to a surface ofdielectric layer 350 that is farthest from handle wafer 348 as shown inphantom in other embodiments. That is, insulating layer 368 may extendalong a vertical length of opening 354. Insulating layer 368 may includeany insulating material discussed herein. At the conclusion of the etchprocess, any remaining mask 352 (FIG. 22) may be removed.

As shown in FIG. 24, a TSV 360 may be formed within opening 354. TSV 360may include a liner layer 364 and a conductive metal layer 366. That is,opening 354 may be substantially lined or coated with liner layer 364.Further, a metal layer 366 may be formed within opening 354 over linerlayer 364 to substantially fill opening 354. Liner layer 364 and metallayer 366 may include any of the materials discussed herein relative toliner layer 142 and metal layer 144 (FIG. 1), respectively. Insulatinglayer 368 may be required as an insulating layer between metal 366 andthe silicon substrate 312, whereas no such insulating layer is needed inthe region of dielectric layer 350, because dielectric layer 350 is notelectrically conducting. After metal layer 366 is formed, metal layer366, liner layer 364, and insulating layer 368 may be planarized to anupper surface of dielectric 350, after removal of any remaining mask.

FIG. 25 shows a resulting integrated circuit structure 390, e.g.,interposer, according to this embodiment of the disclosure. As shown inFIG. 25, conductive pad 372 may be formed as described with reference toFIG. 7. In this embodiment, conductive metal 366 and liner layer 364 arealready exposed. Therefore, there is no need to remove any portion ofinsulating layer 368 as was discussed relative to FIG. 6. Further,additional wiring levels may be formed over conductive pad 372 on backside 304 as discussed with reference to FIG. 8. That is, dielectriclayer 374 may be formed over conductive pad 372. Additionally,connection 380 may be formed within dielectric layer 374, e.g., viapatterning a mask (not shown), etching dielectric layer 374, depositingliner layer 382 and metal layer 384, and planarizing liner layer 382 andconductive metal 384. Connection 380 may be formed such that it contactsconductive pad 372. Further, another conductive pad 388 may be formedover dielectric layer 374 such that it contacts connection 380. Asshown, connection 380 extends from conductive pad 372 toward conductivepad 388 in a direction away from front side 302. Liner layer 382 mayinclude any of the liner layer materials discussed herein. Metal 384 mayinclude any of the conductive metal layer materials discussed herein.

FIGS. 26-31 show wafer 300 undergoing processes according to anotherembodiment of the disclosure. As shown in FIG. 26, during formation ofdielectric layer 350, a wire 420 may be formed within dielectric layer350. For example, dielectric layer 350 may be formed by depositing aplurality of layers (not shown) and a dry or wet surface treatment, suchas a chemical etch, ash, or plasma, may be performed in between eachlayer so that the subsequent layer may have greater adhesion to theprevious layer. During the formation of the plurality of layers, wire420 may be formed therein using standard photolithography techniques.For example, wire 420 may be formed described with respect to wire 220shown in FIGS. 9-11. As discussed herein with respect to wire 220, wire420 may include a liner layer 422 and a metal layer 424. Still referringto FIG. 26, a connection 440 may be formed as described with respect toconnection 240 shown in FIGS. 12-14. As with connection 240, connection440 may include a liner layer 442 and a metal layer 444. Liner layers422, 442 and metal layers 424, 444 may include any liner layer and metallayer materials discussed herein.

Referring now to FIG. 27, mask 352 may be formed to cover dielectriclayer 350 on back side 304 as described with reference to FIG. 21. Mask352 may be patterned and etched to expose dielectric layer 350 tofacilitate the formation of opening 354 within dielectric layer 350 asshown in FIG. 28. After dielectric layer 350 is exposed, opening 354 maybe formed within dielectric layer 350. Opening 354 may be formed, forexample, via etching or laser ablation of dielectric layer 350 to exposesemiconductor layer 312. As shown in FIG. 29, another etch, such as adeep RIE, e.g., a Bosch etch, may be employed to remove portions ofsubstrate 310 and BEOL region 320 to expose handle wafer 348. Deep RIEetching is also known as a pulsed or time-multiplexed etching. During adeep RIE etch, a mode of an isotropic etch is alternated with adeposition of a chemically inert passivation layer (not shown). In thisetch process, mask 352 (FIG. 28) may be eroded or fully removed, anddielectric layer 350 may act as a mask during the etching of substrate310 and BEOL region 320. Additionally, after this second etch process,the chemically inert passivation layer may be removed and insulatinglayer 368 may be formed, e.g., deposited, in opening 354 from dielectriclayer 350 to handle wafer 348. However, while shown and described asbeing deposited form dielectric layer 350 to handle wafer 348,insulating layer 368 may extend from handle wafer 348 to a surface ofdielectric layer 350 that is farthest from handle wafer 348 as shown inphantom in other embodiments. That is, insulating layer 368 may extendalong a vertical length of opening 354. Insulating layer 368 may includeany insulating material discussed herein. At the conclusion of the etchprocess, any remaining mask 352 (FIG. 28) may be removed.

As shown in FIG. 30, a TSV 360 may be formed within opening 354 asdescribed with respect to FIG. 24. TSV 360 may include a liner layer 364and a conductive metal 366 layer. That is, opening 354 may besubstantially lined or coated with liner layer 364. Further, metal layer366 may be formed within opening 354 over liner layer 364 tosubstantially fill opening 354. Liner layer 364, metal layer 366, andinsulating layer 368 may include any of the materials discussed hereinrelative to liner layer 142, metal layers 144, and insulating layer 146(FIG. 1), respectively. After, metal layer 366 is formed, metal layer366, liner layer 364, and insulating layer 368 may be planarized to anupper surface of dielectric layer 350.

FIG. 31 shows a resulting integrated circuit structure 390, e.g.,interposer, according to this embodiment of the disclosure. As shown inFIG. 31, conductive pad 372 may be formed as described with reference toFIG. 7. In this embodiment, metal layer 366 and liner layer 364 arealready exposed. Therefore, there is no need to remove any portion ofinsulating layer 368 as was discussed relative to FIG. 6. Further,additional wiring levels may be formed over conductive pad 372 on backside 304 as discussed with reference to FIG. 7. That is, dielectriclayer 374 may be formed over conductive pad 372. Additionally,connection 380 may be formed within dielectric layer 372, e.g., viapatterning a mask (not shown), etching dielectric layer 374, depositingliner layer 382 and conductive metal 384, and planarization. Connection380 may be formed such that it contacts conductive pad 372. Further,another conductive pad 388 may be formed over dielectric layer 374 suchthat it contacts connection 380. As shown, connection 380 extends fromconductive pad 372 toward conductive pad 388 in a direction away fromfront side 302.

The methods as described above are used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

The descriptions of the various embodiments of the present disclosurehave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

We claim:
 1. A method of forming an integrated circuit structure, themethod comprising: providing a substrate having a front side and a backside, the substrate including: a deep trench (DT) capacitor within thesubstrate extending toward the back side of the substrate, etching thesubstrate on the back side of the substrate to remove at least a portionof the substrate on the back side; forming a first dielectric layercovering the back side of the substrate and extending away from thefront side of the substrate; and forming a through silicon via (TSV)adjacent to the DT capacitor, the TSV extending through the firstdielectric layer toward the front side of the substrate.
 2. The methodof claim 1, wherein the forming of the TSV includes: forming a maskcovering the first dielectric layer over the back side of the substrateand extending away from the front side of the substrate; patterning themask to expose the first dielectric layer over the back side of thesubstrate; forming an opening through the first dielectric layer towardthe front side of the wafer to expose a back-end-of-the-line (BEOL)region on the front side of the substrate; extending the opening throughthe BEOL region toward the front side of the substrate to expose a firsthandle wafer; forming a first liner layer within the opening tosubstantially coat the opening; and forming a first metal over the firstliner layer to substantially fill the opening.
 3. The method of claim 1,further comprising: forming a wire within the first dielectric layerduring the forming of the first dielectric layer, the wire including afirst liner layer and a first metal over the first liner layer prior tothe forming of the TSV.
 4. The method of claim 3, wherein the forming ofthe TSV includes forming the TSV such that the TSV is adjacent to andseparated from the wire in the first dielectric layer.
 5. The method ofclaim 3, wherein the forming of the wire includes forming the wire in aposition within the first dielectric layer that is adjacent to ananticipated position of the TSV.
 6. The method of claim 3, furthercomprising: forming a connection extending from wire away from the frontside of the substrate to a surface of the dielectric layer that isfarthest from the front side of the substrate; and forming a conductivepad over the TSV, the connection, and at least a portion of thedielectric layer such that the wire is electrically connected to the TSVby the connection and the conductive pad.
 7. The method of claim 1,further comprising: forming a conductive pad over the back side of thesubstrate extending away from the front side of the substrate after theforming of the first dielectric layer, the conductive pad covering aportion of the first dielectric layer and the TSV.
 8. The method ofclaim 7, further comprising: forming a second dielectric layer coveringthe conductive pad and the first dielectric layer over the back side ofthe substrate extending away from the front side of the substrate. 9.The method of claim 8, further comprising: forming a connection withinthe second dielectric layer connected to the conductive pad andextending away from the front side of the substrate.
 10. The method ofclaim 1, wherein the forming of the first dielectric layer includesforming a polymer.
 11. The method of claim 1, further comprising:forming a first handle wafer on the front side of the substrate coveringa back-end-of-the-line (BEOL) region and extending away from the backside of the substrate after the providing of the wafer and prior to theetching of the substrate on the back side of the substrate; and removingthe first handle substrate from the front side of the substrate afterthe forming of the TSV.